Digital calculating machine



Sept. 23, 1952 J. E. BARROW 2,611,536

DIGgrAL CALCULATING MACHINE Filed March 26, 1951 (x- L AC. A6. F 7 /V9/.1, N 2.

DELAY. A

A C I C 91 N 2.

DELAY c/w/ 6M2.

0urPur6r -y) INVEIY TOR James Eawano Bmmow Patented Sept. 23, 19522,611,536 DIGITAL QALCULATIN G MACHINE James Edward Barrow, Borehamwocd,England Application March 26, 1951, Serial No. 217,458 1 In GreatBritain March 28, 1950- Claims. (01. 235-c1 UNITED STATES PATENT OFFICEThis invention relates to digital calculating duce a pulse in its ou putonly when both'of its and like logical'machines in which informationinputs simultaneously exhibit pulses. a is represented by sequences ofpulses each se- Where, as is most commonly the case, the quence beingcapable of being interpreted as a pulses to be dealt with are electricalin nature, number in the binary scale, and is concerned 5 for example,voltage pulses, the anti-coincidence I more particularly with thosemachines inwhich and coincidence units preferably are ior'cqmprise eachsequence of pulses isfcaused to occur in a electronic devices such asthermionic tubes'fand single channel with the pulse positions equallythe delay unit either may be one of the known spaced in time in inverseorder to their place delay networks or, as is'preferredgmay belth valuesin the binary number, i. e. with the pulse delay network forming thesubject-matterlo f the position corresponding to the lowest place valueoo-pending' application Serial No. 217:,457 of ven leading. Theinterval'of time between two sucdate herewit V v I f cessive positionsis referred to as a digit time The invention will be clearlyunderstoodfrom and the period of time occupied by a sequence of thefollowing description in which reference is pulses representing thelargest number to be 5 made to the accompanying drawingswherein t t isreferred t as mb r time. Fig. 1 is a diagram illustrating the'broadprin-It is the object of the present invention to prociple upon which theinvention is based, and I vide improved subtracting apparatus for use inFig. 2'is an electrical circuit diagramshowing such machines which shallperform the operation one practical construction of apparatus for ofcombining two such sequences of pulses occurcarrying the invention intoeffect, given as an ring during the same number time in two dif-.example only. 7 ferent channels to form a third sequence of As can beseen from Fig. 1, the apparatus eompulses representing a binary numberwhich is the prises first and second anti-coincidenceunits, differenceof the binary numbers represented by marked respectively AC No. l and ACNo.;2, f. the first two sequences. first and second coincidenceunits,'jma rkedfre-.

According to the invention, subtracting apspectively, C No. l and C No.2,'a delayf unit paratus for machines of the character referred to whichis marked Delay and appropriate pulse comprises two anti-coincidenceunits, two 00- channels connecting the several'units in the incidenceunits, a delay unit operative todelay system shown. by one digit timeany pulse fed thereinto, and The pulse sequence representing the minuendpulse channels so inter-connecting the several is fed in'on the inputchannel marked as andft he units that when the two sequences of pulsesto pulse sequence representing the subtrahend is be combined are bothfed as separateinputs to fed in on the input channel marked z/jt hepulse the first anti-coincidence unit with the sim'ulsequence whichconstitutes the Outpu f t taneous feeding of the sequence representingthe apparatus appearing on the channel, marked subtrahend as one inputto the first coincidence a?'1/, which is the output from the nuit AQunit, the output from the first anti-coincidence No. 2.' v unit willconstitute the one inputto the second If no pulses-occur at it and y,the output'aFy anti-coincidence unit and the second input to alsoexhibits no pulse. Should there be'a pulse the first coincidence'unitthe outputs from the at m and no pulse at y, a pulse l f d y first andsecond coincidence units will constitute 40 C 0 One pu c an el of eachofthe the input to the delay unit, the output from the urn-ts f andthere w n delay unit will constitute the second input to the pulse 111Putput of 0 NO. 1; and, assuming second anti-coincidence unit and'oneinput to a there no pulse from'the' delay the second coincidence unitand the output from f W be a pulse'm i ff? but the secondanti-coincidence unit will constitute 9 pulse m the Output from C L pWhen a pulse occurs at each of theinput chanthe'second input to thesecond coincidence un1t nels .r and y, there will be no pulse in theoutput and. W111 also yield the deslred third sequence of of Na therewill bent) pulse in the p K put of C No. 1; andagain assuming that thereI @1115 speclficatlon, term f is no pulse to come from the delayunit,there dence u i means a two-Input devlce will be no pulse in theoutput :c-y and no pulse rangement adapted to produce a pulse in itsout- 1 be fed by t t delay t put only when e h of its p eXhi-bits a Ifthere is no pulse at input a: and apulseat pulse and the termcoincidence unit means a input y, there will be a pulse in the. outputof two-input device or arrangement adapted to pro- '00 "AC No. 1; therewill be a pulse fed by C No. l

to the delay unit; and, again assuming that there is no pulse to comefrom the delay unit, there will be a pulse in the output :c-y and nopulse will be fed by C No. 2 to the delay unit. The pulse fed to thelatter by C No. 1 will appear at the appropriate inputs to AC No. 2 andC No. 2 at the next digit time and should there be no pulses at :c andyet this instant there will be delivered at output :c-y a further pulsein this next digit time while a further pulse will also be fed by C No.2 into the delay unit.

Without detailing the several stages, it can be stated that theoccurrence of a pulse at the input channel a: and of no pulse at theinput channel y in the next digit time to that in which a pulse was fedto the delay unit will result in no pulse in the output III-y and thefeeding of no pulse to the delay unit. Similarly, the other possibleoccurrences will also yield the appropriate outputs.

,Fig. 2 illustrates a circuit which maybe utilized with great advantagein carrying the invention into practice in those cases where. the pulsesare voltage pulses. The input channels are again markeda; and y andtheoutput channel is again ma d: 7

Those portions which correspond to the blocks in the diagram of Fig. lare correspondingly marked in Fig. 2; The twojanti-coincidence unitsfollow each other at the left-hand side of the circuit diagram and arethen. iollowedby the delay unit which is succeeded by the two,coincidence units. Inv each ofv the antircoincidence units the value ofthe resistance R1. is made very much greaterthan that of either or" theresists ancs R2 whichare equal to. each other. The unidirectionalconducting devices indicated at D may be diodes or. germanium or. othersuitable crystals. Both the anti-coincidence uhitsoperate in a mannerwhichwill beclearfrom a .consideration of the circuit details withoutdetailed explanation 116136.. If a pulse is supplied in the input :rlandno. pulse is supplied. in the input 1/ to the first anti-coincidenceunita pulse is derived in the output 01 of this-unit. The same resultissecured if a pulse iszsupplied at theinput y and no pulse is suppliedat the input at. Should a pulse be supplied atthe input :2 and anotherat the input 3 simultaneously, there will be no pulse in the output 01from this first anti-scointhe passage of any pulse which may bedelivered to the delay unit from the output 03 of the coincidence units.Since the delay unit functions due to the inclusion of inductances L1and L2 in its input and output sides, respectively, the shape of anypulse which is delivered by the delay unit will have been distorted fromthe square-topped pulses shape which is normall employed in suchcircuits. The output from the delay .unit is therefore employed-tocontrol agate G1 to which properly shaped pulses are supplied from anywellknown clock-pulse generator, so that the efiective output from the.delay unit will consist of properly cidence unit. As has been said,similar considerations apply to the second antircoincidence unit, theoutput ofv which (markedOz) is also the output from the completeapparatus.

. .The manner in. which the coincidence units function will be clearfrom a consideration of a the circuit illustrated, it being understoodthat the valves 01 and C2 are short suppressor-base pentodes and it willbe: seen that there'willbe no pulse inthe common output Q3-Of theseunits unless a pulse is'deliveredbythe one or other coincidence unitpandfurther that neither unit will deliver a pulse unless there is a pulsein each of its two inputs simultaneously.- The two inputs to the firstcoincidence 'unit are the output from the first anti-coincidence unitand the y input whereas those for-the second. coincidence unit are.thBIOlltPlltffOl'fi'sthB second anti-coincidence unit and the. outputOiof the delay unit. The output 04 from thelatter is also supplied as oneof the inputs to the second anti-coincidence unit.

The delay unit shown is that which is described in the specification of'co-pending application Serial No. 217,45'Tof even date herewith, and isarranged to cause a delay of one digit time in shaped pulses.

Provision ismade for D. C. restoration at appropriate points in thecircuit, as will be appreciated from a consideration of the latter.

What I claim is:

l.- In a binary digital calculating machine, a subtraction circuitcomprising a first and a second anti-coincidence unit, a first and asecond coincidence unit, a. delay unit, apulse input channel to thefirst anti-coincidence unit for each of the two pulse sequencesrepresenting respectively. the

numbers whosedifferenceis to be found, and

a pulseinput channel to one of the inputs. of the first coincidence unitfor feeding the subtrahend thereto simultaneously with its-being red tothe said first anti-coincidence unit, and pulse transmission channelsinterconnecting the said units as follows: va channel connecting theoutput'frcm the first anti cqincidence unit to one of the inputs ofthesecond anti-coincidence unit; a channel connecting the output from thefirst anti-coincidence unit to. the other of. the inputs of the firstcoincidence. .unit; a channel connecting the outputs of Bach:ofwthecoincidence units to the delay unit; .;a channelconnecting theoutput of the delay unit towthe other input of the secondanti-coincidence: unit and to one of the inputs of theisecondzcoincidence unit; and a channelconnecting the: output of thesecond anti.- coincidence unit to the otherv input of the secondcoincidence unit, andia resultant outputchannel from the output of thesecond antiscoincidence unit.

2. In asubtractioncircuit as claimed in claim 1, an anti-coincidence.unit comprising a pair of similar multi-electrode thermionic tubes eachhaving a control grid constituting a respective input to the unit,--apair of equal resistances constituting respectively the'anode loadsofthe tubes, and a pair of unidirectional conducting devices similarlyconnected between the respective anodes and a common output channel. 3.An anti-coincidence unit as claimed inclaim 2 wherein the cathodecircuits of the two tubes are commoned and "the said common circuitincludes a resistance whose value is large compared with thatof theanode load resistances.

l. In a subtraction circuit as claimed in claim 1, a coincidenceunitcompris-ing a thermionic tube having at least-two grids, each ofsaid grids constituting apu'lse 'input to the unit.

5. In a sub-traction oircuitas claimedin claim 1, a pair of coincidenceunits each comprising a thermionic tube having at least two gridsconstituting the inputs tov the :unit, a common anode load resistancefor both tubes, and a common output channel frorn the anodes of bothtubes.

' No reicrences cited. I

